SOI (“silicon on insulator”) technology is a beneficial alternative when compared with the “bulk silicon” approach, in particular for high-frequency component manufacturing, of transistors, for example.
There are simultaneous trends in integrated circuits towards a constant reduction in the dimensions of integrated circuits and towards an increase in the density of the latter. The reduction in the dimensions of integrated circuits is accompanied by level-to-level alignment specifications that are increasingly difficult to achieve. In particular the ability to align contacts relative to gates within an advanced transistor architecture is desired. In this context a technique for the self-alignment of contacts relative to gates is beneficially implemented.
There is a method known in the state of the art for making integrated circuits with self-aligned contacts using a “gate-last” approach, as described in document WO 2011/090571 A2. A method for making a transistor with a “gate-last” type approach comprises a step for making a gate zone within a sacrificial stack, then a step for replacing the sacrificial stack with the final gate stack. Another possible approach is the “gate-first” approach. In the case of a “gate-first” approach, a gate zone is made directly in a gate stack, which will make up the gate zone in the final integrated circuit. A “gate-first” approach does not require the use of sacrificial materials and is therefore beneficially less costly to implement than a “gate-last” approach. Moreover, SOI technology favours “gate-first” type approaches in the manufacture of components, since the specifications in terms of threshold voltage are slightly less restrictive than in “bulk” type approaches.
A method 100 for making MOSFET transistors with self-aligned contacts in a “gate-first” approach in accordance with the state of the art is described, for example, in FIGS. 1 to 12. FIGS. 1 to 12 are described jointly.
A first step 101 in the method 100 is shown in sectional view in FIG. 1a and in a top view in FIG. 1b. The sectional view is along a first plane P1 with centre O and orthogonal axes X and Z; the top view is along a second plane P2 of centre O and orthogonal axes X and Y. The second plane P2 is perpendicular to the first plane P1. According to the first step 101, a start is made from a substrate 10 of the SOI type which incorporates shallow trench insulation (STI). The substrate 10 comprises a first layer 11 of Si, on which an insulating layer 12 of SiO2 extends, also known as Box (“buried oxide”). The insulating layer 12 has a thickness measured along the Z axis which is typically less than or equal to 25 nm. A thin layer 13 of Si extends over the insulating layer 12. The thin layer 13 of Si has a thickness measured along the Z axis which is typically less than 5 nm. The thin layer 13 of Si forms an active zone. The substrate 10 incorporates STI insulation zones 14. The substrate 10 thus has alternating insulation zones 14 and active zones 13.
A second step 102 of the method 100 is illustrated as a sectional view in FIG. 2. The sectional view is along the first plane P1.
According to a second step 102, a gate stack 15 is deposited on the substrate 10. The gate stack 15 can typically comprise;                a first layer 15-1 of a high-k dielectric, with the first layer 15-1 extending over the substrate 10;        a second layer 15-2 of titanium nitride, with the second layer 15-2 extending over the first layer 15-1;        a third layer 15-3 of polysilicon, with the third layer 15-3 extending over the second layer 15-2;        a fourth layer 15-4 of a dielectric, for example a nitride, with the fourth layer 15-4 extending over the third layer 15-3;        
A third step 103 in the method 100 is shown in sectional view in FIG. 3a and in a top view in FIG. 3b. The sectional view is along the first plane P1 and the top view is along the second plane P2.
According to the third step 103, gate zones 16 are defined in the gate stack 15, for example using lithography and anisotropic etching of the gate stack 15. Each gate zone 16 has, in the example shown, a width of 14 nm measured along the X axis. The separation distance along the X axis between two consecutive gate zones 16 is 64 nm in the example shown.
First insulating spacers 17 are then made around each gate zone 16.
A fourth step 104 in the method 100 is shown in sectional view in FIG. 4a and in a top view in FIG. 4b. The sectional view is along the first plane P1 and the top view is along the second plane P2 . According to the fourth step 104, a start is made by using a first mask M1 to protect a region which is later intended to form pMOS transistors in the example shown. Then first drain and source zones 18 are made which are n-type in the example shown. The first mask M1 is removed at the end of the third step 103.
A fifth step 105 in the method 100 is shown in sectional view in FIG. 5a and in a top view in FIG. 5b. The sectional view is along the first plane P1 and the top view is along the second plane P2. According to the fifth step 105, a start is made by using a second mask M2 to protect a region which is later intended to form nMOS transistors in the example shown. Then second drain and source zones 19 are made which are p-type. The second mask M2 is removed at the end of the fifth step 105.
A sixth step 106 in the method 100 is shown in sectional view in FIG. 6a and in a top view in FIG. 6b. The sectional view is along the first plane P1 and the top view is along the second plane P2. According to the sixth step 106, second insulating spacers 20 are made around the first insulating spacers 17. The second insulating spacers 20 are made from a dielectric material, for example a nitride. Other spacers in contact with the second spacers could also be made.
A seventh step 107 of the method 100 is shown in sectional view in FIG. 7. The sectional view is along the first plane P1. According to the seventh step 107, the fourth layer 15-4 of dielectric, located at the top of each gate zone 16, is removed thus exposing the third layer 15-3 of polysilicon. A layer 21 of a material which is suitable for silicidation using, for example, a layer of nickel Ni, is then deposited on the surface of the device, covering in particular each third layer 15-3 of gate zones 16 as well as the first source and drain zones 18 and the second source and drain zones 19.
An eighth step 108 in the method 100 is shown in sectional view in FIG. 8a and in a top view in FIG. 8b. The sectional view is along the first plane P1 and the top view is along the second plane P2. According to the eighth step 108, heat treatment is carried out so as to cause, starting from layer 21, the formation of zones 22 of silicide at the surface of each third layer 15-3 of the gate zones 16 as well as the first drain and source zones 18 and the second drain and source zones 19. The residual material of the layer 21 is then removed by etching which is selective in relation to the material of the second spacers 20.
A ninth step 109 of the method 100 is shown in sectional view in FIG. 9. The sectional view is along the first plane P1. According to the ninth step 109, the deposition of a layer 23 of a pre-metal dielectric (PMD) material is carried out at the surface of the entire device. Then a polishing step 23 of the PMD dielectric material is carried out, for example using a chemical-mechanical polishing step (CMP).
A tenth step 110 of the method 100 is shown in sectional view in FIG. 10. The sectional view is along the first plane P1. According to the tenth step 110, a third mask M3 is deposited on the layer 23 of the PMD dielectric material. The third mask M3 may be, for example, a layer of resin. A lithography step is then carried out on the third mask M3 in order to define the zones to be etched in the PMD dielectric material. At the end of this lithography step the third mask M3 is preserved above the insulation zones 14 and therefore protects the insulation zones 14.
An eleventh step 111 of the method 100 is shown in sectional view in FIG. 11a and in a top view in FIG. 11b. The sectional view is along the first plane P1 and the top view is along the second plane P2. According to the eleventh step 111, anisotropic etching of the layer 23 of PMD dielectric material which is not protected by the third mask M3 is carried out, for example by means of a reactive-ion etching (RIE) method. The third masque M3 is then removed, for example by a stripping method.
A twelfth step 112 of the method 100 is shown in sectional view in FIG. 12. The sectional view is along the first plane P1. According to a twelfth step 112, a layer 24 of pre-contacts metal is deposited. The pre-contacts metal may be, for example, tungsten.
A thirteenth step 113 of the method 100 is shown in sectional view in FIG. 13. The sectional view is along the first plane P1. According to the thirteenth step 113, a step for polishing the layer 24 of the pre-contact metal is carried out, for example by CMP chemical-mechanical polishing. This polishing step is done to break the circuit between the gate zones 16, the first source and drain zones 18 and the second source and drain zones 19. This step for breaking the circuit however has the drawback of also removing zones 22 of silicide previously formed on the surface of gate zones 16.
The method 100 of the state of the art described above shows the difficulty experienced in obtaining self-aligned contacts in a “gate first” approach whilst ensuring silicised gates are obtained.